A memory system is disclosed which is characterized by high speed data throughput on a channel, or on a number of channels, between a memory controller and associated memory devices.
During the last several decades, memory technology has progressed dramatically. The density of commercial memory devices, taking Dynamic Random Access Memory (DRAM) as a convenient example, has increased from 1 Kbit to 64 Mbits per chip, a factor of 64,000. Unfortunately, memory device performance has not kept pace with increasing memory device densities. In fact memory device access times during the same time period has only improved by about a factor of 5. By comparison, during the past twenty years, microprocessor performance has increased by several orders of magnitude. This growing disparity between the speed of microprocessors and that of memory devices has forced memory system designers to create a variety of complicated and expensive hierarchical memory techniques, such as Static Random Access Memory (SRAM) caches and parallel DRAM arrays. Further, now that computer system users increasingly demand high performance graphics and other memory hungry applications, memory systems often rely on expensive frame buffers to provide the necessary data bandwidth. Increasing memory device densities satisfy the overall quantitative demand for data with fewer chips, but the problem of effectively accessing data at peak microprocessor speeds remains.
Massively parallel DRAM arrays having relatively wide buses have been a typical response to the demand for more data bandwidth at higher access speeds. FIGS. 1 and 2 illustrate generic, conventional memory systems having a memory controller 10 connected to a number of memory devices 12 via a wide bus structure. In FIG. 1, each memory device 12 is connected to memory controller 10 via sixteen (16) dedicated bus lines. (Not all bus lines are individually shown for the sake of clarity). Assuming four memory devices in the system of FIG. 1, the data bus is 64 lines wide. This structure allows the memory controller to directly send and receive data from a specific memory device without interference from any other memory device. However, each data bit so sent and received requires the addition of another data line to the bus.
In the memory system shown in FIG. 2, a single 64 line, data bus is shared by four 64-bit memory devices. In the example shown in FIG. 1, accessing four 64-bit memory devices would require a 256 line wide data bus. Thus, the structure of the memory system shown in FIG. 2 represents an advance over that of FIG. 1. However, the reduction in relative data bus width comes with some additional overhead. In the memory system of FIG. 2, each memory device receives an individual set of control signals 14 from memory controller 10. These separately transmitted signals are required to regulate memory device access to the common data bus lines.
As can be seen from the foregoing examples, conventional memory systems use a large number of data lines, or a relatively wide bus. The term xe2x80x9cline(s)xe2x80x9d is used to describe the physical means by which data bits are electronically communicated from one point to another in a system. A line may take the form, alone or in combination, of a printed circuit board (PCB) strip, metal contact, pin and/or via, microstrip, semiconductor channel, etc. A line may be single or may be associated with a bus. A xe2x80x9cbusxe2x80x9d is a collection, fixed or variable, of lines, and may also be used to describe the drivers, laches, buffers, and other elements associated with an operative collection of lines. In the description of the invention which follows, a bus may communicate control information, address information, and/or data. In the foregoing examples of conventional memory systems, the bus was assumed to transmit data only. Address and control information is separately transmitted by additional lines or buses.
Such massively parallel, or wide buses, are required in conventional memory systems due to the slow access speed of the individual memory devices. Wide buses have long been associated with implementation and performance problems, such as excessive power consumption, slow speed, loss of expandability and design flexibility, etc. As a result, bus multiplexing of control, address and/or data information has become commonplace. Multiplexing, in any of its varied forms, effectively xe2x80x9ctime-sharesxe2x80x9d a bus between a number of devices.
Multiplexing allows reduction in bus size. It also greatly increases system complexity. Such complexity often results in increased memory system rigidity. That is, once implemented in all its complexity, the integration of a new function into the bus-multiplexing memory system becomes extremely difficult. In particular, memory system designers continue to face enormous challenges in increasing data throughput while minimizing system complexity, and maintaining system reliability.
The present invention provides a high-speed memory system having enhanced modal functionality without a significant corresponding increase in system complexity.
Thus, in one aspect, the present invention provides a memory system operating in either a first mode or a second mode of operation and comprising; a memory controller connected to memory devices via at least one channel, the memory controller communicating at least one command to each one of memory devices via the at least one channel, such that while the memory system operates in the first mode, one of the memory devices responds to the at least one command to accomplish transfer of data between the one memory device and the memory controller during a first time period; and while the memory system operates in the second mode, a plurality of the memory devices responds to the at least one command to accomplish transfer of data between the plurality of memory devices and the memory controller during the first time period.
In another aspect, the present invention provides a memory system operating in either a first mode or a second mode of operation and comprising; a memory controller connected to memory devices via at least one channel, the memory controller communicating at least one command to each one of memory devices via the at least one channel; such that while the memory system operates in the first mode, one of the memory devices responds to the at least one command to change operating states, and while the memory system operates in the second mode, a plurality of the memory devices responds to the at least one command to change operating states.
The present invention in various configurations also allows a plurality of relatively low bandwidth memory devices to combine in operation to produce high bandwidth data output.
Thus, in one aspect, the present invention provides a memory system comprising; a memory controller connected to at least one channel, and memory devices connected to the at least one channel, wherein at least one of the memory devices is a low bandwidth device being individually incapable of communicating a first data block with the memory controller during a first time period, wherein the memory controller communicates control information to at least a first plurality of the memory devices via the at least one channel, and in response to the control information, the first plurality of memory devices, as a multiplexed group on the channel, communicates a first data block between the memory controller and the first plurality of the memory devices during a first time period.
In still another aspect, the present invention provides a memory system comprising; a memory controller connected to at least one repeater via a main channel, wherein each repeater connects a first plurality of memory devices via at least one auxiliary channel, and wherein each one of the first plurality of memory devices is a low bandwidth device individually incapable of communicating a first data block with the memory controller during a first time period, and wherein the memory controller communicates control information to the first plurality of the memory devices via the at least the main channel, the at least one repeater, and the at least one auxiliary channel, and in response to the control information, the first plurality of memory devices, as a multiplexed group on the channel, communicates a first data block between the memory controller and the first plurality of the memory devices during a first time period.
In a related aspect to the foregoing, the present invention provides a memory system capable of selectively operating in first and second modes comprising; a memory controller, memory devices, and a channel connecting the memory controller with the memory devices, wherein each one of the memory devices is capable of operating in at least a first and a second power state, the first power state consuming more power than the second power state, such that while the memory system is operating in the first mode, the memory controller generates a first power down device identification (ID) unique to one of the memory devices, whereby the one memory device upon receiving the first power down device ID will transition from the first power state to the second power state, and while the memory system is operating in the second mode, the memory controller generates a second power down device ID having the same structure as the first power down device ID, such that a plurality of memory devices upon receiving the second power down device ID transition from the first power state to a second power state.
In another related aspect, the present invention provides a memory system comprising; a memory controller connected to a data bus comprising a plurality of lines and generating one or more command packets, a group of memory devices, wherein each memory device in the group is connected to at least one of the plurality of lines, each one of the memory devices in the group comprising a circuit responsive to the one or more command packets from the memory controller, such that the group of memory devices combine to output a first data packet during a first time period by multiplexing data onto the data bus during the first time period.
In still another related aspect, the present invention provides a method of reading data in a memory system during a first time period, the memory system comprising a memory controller connected to memory devices via a data bus having multiple data bus lines, the method comprising; communicating at least one command packet from the memory controller to a plurality of the memory devices, for each memory device in the plurality of memory devices, seizing at least one data bus line during the first time period and returning data to the memory controller via the at least one data bus line in response to the at least one command packet.
In still another related aspect, the present invention provides a method of reading a first block of data in a memory system during a first time period, the memory system comprising a memory controller connected to memory devices via a data bus having multiple data bus lines, the first time period comprising sequence of second time periods, and the method comprising; communicating at least one command packet from the memory controller to a plurality of the memory devices, during each second time period, outputting a second block of data smaller than the first block of data from a selected memory device in the plurality of memory devices via the data bus, such that a combination of the second blocks output during the first time period comprises the first data block.